The present invention relates to a technology on program control in multiprocessor systems.
FIG. 17 shows examples of conventional configurations of processor systems realizing parallel operation of a plurality of arithmetic units and registers. In a multiprocessor system shown in FIG. 17(a) threads (processing units) in processors 110 and 120 are operated independently, in general. This system is therefore considered to exhibit high throughput for applications executing a plurality of independent threads in parallel.
In a very long instruction word (VLIW) system shown in FIG. 17(b), a single instruction code includes description of fields for controlling a plurality of arithmetic units and registers. This system is therefore considered to exhibit high throughput for a single thread.
Superiority of one of the processor systems described above over the other differs depending on the application. Therefore, the processor system to be adopted should preferably be determined according to the features of threads in the application.
Problem to be Solved
In recent embedded systems, various types of processing exist in a mixed state, and therefore it is difficult to determine what processor system should be adopted. For example, there is a case of including both processing of a single thread, which requires very high throughput to realize high-speed real-time processing, and parallel processing of a plurality of threads, which does not require so high throughput. In this case, whatever processor system is adopted, it will never be optimum. In most cases, therefore, a margin is provided for the throughput of any processor system adopted, and this poses a big barrier to attainment of lower power consumption and higher speed of the system.